The power and flexibility of personal computers has grown tremendously in terms of their use in many areas. Personal computers typically contain a microprocessor chip, random access memory and non-volatile memory provided by semi-conductor memory chips. Non-volatile memory retains previously stored information within the memory even when power is removed from the chip. One type of non-volatile memory, which will be referred to as flash memory, uses floating gate technology and may be electrically erased rather than erased by an external energy source such as ultraviolet light. Flash memories may also be programmed electrically by using a high-voltage programming current.
Flash memories have used complementary metal-oxide semiconductor (CMOS) level-shifting circuits to switch to the high voltage required for programming operations. In a typical flash memory, the high voltage required for programming operations is controlled by 5-volt logic signals. These signals require a level-shifting circuit for switching to the higher voltages needed for programming, normally in the range of 10 to 13 volts. A typical level-shifting circuit for CMOS devices is shown in FIG. 1. The circuit is symmetrical, comprising a cascode configured pairs of P-channel and N-channel transistors. A cascode configuration is normally used to avoid snapback problems with metal-oxide semiconductor field effect transistors (MOSFET), such as transistors 10, 12, 14 and 16, during high voltage switching. A disadvantage to this type of circuit is that one of the P-channel transistors, either 18 or 20, is coupled to Vss (ground) at its drain when their respective NMOS transistors are conducting, which results in a high reverse bias voltage (Vpp) on the drain to N-well junction. Another disadvantage is that one of the P-channel devices, either 14 or 16, is coupled to high voltage (Vpp) across its gate oxide while the device is activated, which may result in the deterioration and failure of the flash memory over time.
FIG. 2 illustrates a second known circuit which includes transistors 30 and 34 having their respective N-wells coupled to their sources. This approach limits the drain to N-well junction voltage to a level corresponding to a bias voltage (Vpt) minus the threshold voltage of the P-channel transistor. While this approach does limit the drain to N-well voltage on the P-channel transistors, one of the P-channel devices, either 32 or 36 depending on which of the devices is activated, still experiences a"Vpp" voltage differential across its gate oxide. As a result, the risk of deterioration and failure of the flash memory still exists.
Therefore, a need exists for a level-shifting switch which minimizes P-channel transistor exposure to high voltages on drain to N-well junctions and gate oxides, particularly in switching applications where the switch is known to be in one of its two logic states for most of the time.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, an asymmetric switch arranged to minimize transistor exposure to high voltage is provided. The switch, in a particular embodiment, comprises a pair of P-channel transistors with both N-wells coupled back to the programming voltage source and a pair of P-channel transistors with independent N-wells. Two pairs of N-channel transistors and an inverting circuit provide complementary input voltages to the switch. The P-channel and N-channel transistors may be biased by the same voltage or separate voltages.
In one embodiment, the present invention comprises: first and second P-channel MOSFETs in cascode connection with the first P-channel MOSFET source and first and second P-channel MOSFET N-wells being coupled to a first voltage; third and fourth P-channel MOSFETs in serial connection having independent N-wells, with the third P-channel MOSFET source being coupled to the first voltage and the gates of the second and fourth P-channel MOSFETs being coupled to a second voltage; the first P-channel gate being coupled to the fourth P-channel MOSFET source, and the third P-channel MOSFET gate being coupled to the second P-channel MOSFET drain forming an output line; and first, second, third, and fourth N-channel MOSFETs, the first and second N-channel MOSFETs being in serial connection with the output line, the third and fourth N-channel MOSFETs being in serial connection with the fourth P-channel MOSFET drain, the gates of the second and fourth N-channel MOSFETs being coupled to the second voltage, and the gates of the first and third N-channel MOSFETs being coupled to receive complementary input signals.
The above summary of the present invention is not intended to present each embodiment or every aspect of the present invention. This is the purpose of the figures and the associated description which follow.